(1) Field of the Invention
The present invention relates to a semiconductor recording device such as a memory card, a control method thereof, and a semiconductor recording system, and in particular, to a control method which reduces variation in data holding characteristics of a non-volatile memory within the semiconductor recording device and deterioration of the non-volatile memory caused due to repeated writings.
(2) Description of the Related Art
Conventionally, a semiconductor recording device, such as an SD (Secure Digital) card that is a card-type recording medium incorporating a flash memory, is very small and thin. Due to its handiness, such semiconductor recording device is widely used for recording data, such as images, in a digital camera, a portable equipment and so on.
The flash memory in the semiconductor recording device is a memory which includes physical blocks of a uniform size, and which can erase data on a physical block basis. To address a demand for an increased capacity in recent years, a multi-level flash memory capable of storing data of two bits or more in one cell has been commercialized.
Reference is made to a four-level flash memory as an example of the multi-level flash memory, with reference to FIG. 1. FIG. 1 is a diagram showing relationship between an accumulating state of electrons in a floating gate of the four-level flash memory and a threshold voltage (Vth).
As shown in FIG. 1, in the four-level flash memory, the electron accumulating state in the floating gate is managed in four states according to its threshold voltage (Vth). In FIG. 1, the state where the number of accumulated electrons (the charge amount of electrons) is lower and an electric potential is lowest is an erase state. This state is defined as (1, 1). As more electrons are accumulated, the threshold voltage discretely rises. These states are defined as (1, 0), (0, 0) and (0, 1). Since the electrical potential rises in proportion to the number of accumulated electrons in such a manner, the electron accumulating state can be controlled in four states so as to fall below a predetermined threshold value. Accordingly, data of two bits can be recorded in one memory cell.
However, the four states are identified depending on the charge amount of electrons in the four-level flash memory. Therefore, the differences of the threshold voltage between each state in the four-level flash memory are smaller than the difference of the threshold voltage between the states in a binary flash memory.
When data writing is repeated, the gate oxide film is slightly damaged due to injection and extraction of electrons. The repeated damages generate many electron traps, which results in a decrease in the number of electrons accumulated in the actual floating gate. Furthermore, the number of electrons accumulated in the floating gate decreases in proportion to miniaturization in the semiconductor process rules; and thus, advanced miniaturization of the flash memory increases the influences of the electron traps.
With advent of multi-value record which supports increased capacity of flash memories and miniaturization in the semiconductor process rules, deterioration of data holding characteristics of the flash memories has become a noticeable problem.
As a method for improving data holding characteristics of the flash memories, there is a proposed method in which error correction capability is enhanced.
For example, Japanese Unexamined Patent Application Publication No. 2006-18373 discloses a technique for enhancing error correction capability and reducing deterioration in data holding characteristics of the flash memories. In this technique, blocks in different chips in a flash memory are associated with one another, a plurality of associated blocks are handled as a common group, and one block in the group is assigned to a parity block for user data written into another block in the group.
There are two conventional schemes for associating a logical address issued by a host device, and a user-data write area and a parity-data write area that correspond to the logical address.
In the first conventional scheme, in a semiconductor recording device incorporating flash memory chips therein, one flash memory chip is used as a write area for parity data and the other flash memory chips are used as a write area for user data (this scheme corresponds to RAID4 (Redundant Arrays of Independent Disks 4) of a hard disk).
In the second conventional scheme, a user-data write area and a parity-data write area each are divided into pages of a flash memory, flash memory chips corresponding to the parity-data write area are sequentially moved. As a result, parity data is approximately evenly assigned to the respective flash memory chips, and a table is recorded which stores unique correspondence between parity data and logical addresses issued by the host device (this scheme corresponds to RAID5).
When applying such structure of the semiconductor recording device to a removable semiconductor recording device such as a memory card, a first scheme, in which a parity processing circuit is included in a memory card, and a second scheme, in which a parity processing circuit is provided outside a memory card, are possibly used.
In the first scheme in which the parity processing circuit is included in the memory card, a dedicated hardware is required; and thus, a problem exists in that inexpensive memory cards cannot be provided. On the other hand, the second scheme in which the parity processing circuit is provided outside the memory card can be achieved relatively inexpensively by using the CPU of the host device for parity processing.
In the case where the second scheme is applied to a general-purpose computer, the following two schemes (a) and (b) are possibly used. The scheme (a) is a scheme where parity data is generated by an application and recorded as a file. The scheme (b) is a scheme where parity data is generated by a dedicated driver of a memory card and recorded.
A problem exists in the scheme (a) that user data and its related parity data are not written in association with a logical address having a given relationship; and thus, the scheme (a) is not effective to improve data holding characteristics of the flash memory.
In the scheme (b), user data and its related parity data are written in association with a logical address having a given relationship.
However, in the case where user data is overwritten by a general-purpose driver which does not have a function to process parity data, onto a memory card to which parity data is already written by a dedicated driver, the relevance between the user data written by the general-purpose driver and the written parity data is lost. In this case, if an error generated in the user data after being overwritten is corrected by parity data which has no relevance with the user data, the correction results in a false correction.